The EN29A0QI offers very tight DC accuracy, combined with remote ground sense to meet the challenging tolerance requirements for high speed transceivers in FPGAs and ASICs. The internal inductor is sized to provide very low output switching ripple while the package is designed for low EMI. The control loop topology is based on low impedance voltage mode control combined with a high-performance error amplifier for excellent load transient performance. The wide bandwidth control loop, combined with the low impedance voltage mode control can enable a significant reduction of expensive bulk decoupling capacitors. The output voltage ripple plot shown here was taken for an input voltage of 12V and an output voltage of 1.05V which is a typical high-speed transceiver voltage. The output capacitor arrangement is that of a typical application where the local output filter capacitance consists of four 47mF ceramic capacitors in addition to a total downstream bulk decoupling capacitance of about 470mF. This bulk decoupling capacitance is representative of the total decoupling capacitance located at the pins of the FPGA, ASIC or other load. Notice that at a full oscilloscope bandwidth of 500MHz, the output voltage ripple is less than 4mV peak-to-peak. Even though this plot is for an output load current of 5A and a PWM switching frequency of 1MHz, the designer can expect similar performance for other combinations of load currents and switching frequencies. The load transient plot shown here was also taken for an input voltage of 12V and an output voltage of 1.05V. The output capacitor arrangement is the same as it was for the output voltage ripple plot. The output load current was stepped from 5A to 10A which is representative of a 50% load step, and as can be seen from this plot, the output voltage deviation is less than ±15mV. As was the case for the output voltage ripple, one can expect a similar level of performance for other switching frequencies and other 50% load current step values (for example, a load current step from 2.5A to 7.5A). As one might expect, the output voltage deviation will increase as the load current step values are increased (for example, a 100% load current step from 0A to 10A). This increase can be partially mitigated by increasing the bulk load decoupling capacitance located at the pins of the FPGA, ASIC or other load.