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Examining the details of the FPGA from the previous system block diagram, this slide shows the block diagram of what the single-chip FPGA-based IP camera might look like. The image processing pipeline is shown at the bottom of the figure, with the blue line representing the data pipeline. The first three blocks come from Apical, Ltd. (acquired by Arm®) and represent the sensor interface, the image sensor pipeline (ISP) including two of the 3A functions (auto exposure and auto white balance), and iridix, Apical’s (acquired by Arm®) premier algorithm enabling WDR image data to be compressed to a standard 8-bit video path while preserving contrast through spatial local tone mapping. Apical (acquired by Arm®) also provides sinter, their 2D noise reduction core that is quite helpful in removing CMOS sensor typical fixed pattern noise. Note that the remaining 3A algorithm is auto focus. While Apical (acquired by Arm®) does not provide auto focus IP, their pipeline does output statistics that a processor, either Nios® II or external, can use to determine focus settings and drive the lens focus motor. Flexible and high-quality image scaling is offered in Intel's® popular “Video IP Suite”. Several of Intel's® IP partners offer H.264 encoding at 720p30 (720 lines, 30 frames per second) performance or higher (up to 720p60 in a Cyclone® III or IV FPGA). And, Intel® offers a triple-speed Ethernet MAC capable of 10/100/1000 Mbps operation. In the control plane or upper part of the chip, the Nios® II processor also manages the data pipeline, runs the Ethernet stack and assists in the 3A algorithms. Finally, a hardware PWM controller could be implemented to control stepper or BLDC motors for pan and tilt operation of the camera.
