Intel Quartus Prime Software: Unleashing Design Potential

2023-08-04 | By DWARAKAN RAMANATHAN

License: General Public License

The world of digital design is ever-evolving, and engineers constantly seek powerful tools that can optimize their productivity and unlock the full potential of their designs. Intel Quartus Prime Software emerges as a robust and versatile solution, equipping designers with a comprehensive suite of development tools tailored for FPGA (Field-Programmable Gate Array) and CPLD (Complex Programmable Logic Device) designs. In this blog post, we delve into the essence of Intel Quartus Prime and uncover the capabilities that make it an indispensable companion for digital designers.

The Intel Quartus Prime Software can be found here: FPGA Design Software - Intel® Quartus® Prime

Once you have reached the webpage for downloading the Intel Quartus Prime software, you will have to choose between three different editions of the software. One among the three has free access and requires no license i.e. The lite Edition of the Software. On clicking the boxes provided below the lite edition for your convenient operating system, you will reach another page asking you to choose between multiple downloads or individual files.

I would prefer you to choose Multiple downloads which will contain the files required for all the devices like:

• Intel Arria II
• Intel Cyclone IV
• Intel Cyclone 10 LP
• Intel Cyclone V
• Intel MAX II/V
• Intel MAX 10 FPGA

Another way to download the software would be by selecting the required files and devices that you require. This method will also require less space.

In this article, we will use the MAX 10 FPGA, so select the Intel Quartus Prime(Includes Nios II EDS) and the MAX 10 FPGA Device files to download. After downloading the files, please install the software and select the required checkboxes after reading it well (Skipping the installation process). Once the software is installed, it will look something like this.

Let's now start working on our new project. To create a new project, click on the "New Project Wizard" as shown in the picture above. It will open a new window asking for the project title and the name of the top-level entity.

Type the name of the project as you wish. In this case, I am naming the project “getting started” since this blog will contain very basic steps that you should know before using the software. You will see that the name of the entity will be taken automatically,  do not change it. Click on "Next" once you have completed naming the project.

Select Empty project because we are creating a new project without any template. Click next to continue.

Since we are going to create a new file, we do not want to add any files. So, click next to continue.

This is an important step. You need to select the device as per your needs. For now, I am selecting the MAX 10(DA/DD/DF/DC/SA/SC/SL) as my device and clicking next (Note: the pin count and package must be selected as mentioned in the device manual).

We will look at the tools in a separate article because this part will need one. For now, leave everything as "<None>" and click Next.

On this page, you will see everything that you have selected, or the files uploaded previously. Find whether you have selected the device name and specifications as per the device manual, and it is not specified here. Click "Finish" after doing so, and you will land a page something like this.

You will see your project opened in the project navigator and ready to be added with files. It will not have any files in it for now because we haven't added any. To add a file, click on "File" and "New", then select Verilog because we are going to create a half adder using Verilog (Hardware Description Language).

To learn Verilog: Verilog Tutorial for Beginners 

After selecting Verilog and clicking "OK" you will have opened a new window in the Workspace of the software. So, to create an adder, the code goes like this:

module gettingstarted(a,b,sum,carry); 
input wire a,b; 
output wire sum,carry; 
assign sum=a^b; 
assign carry=a&b; 
endmodule

Click on "Analyze Current File" to check if there is any error in the code. The software provides you with an inbuilt compiler and a lot of tools that you can rely on.

You will receive a message stating "0 errors" if there are no errors in the code. Now, you have created a file inside your project, which is ready to be synthesized and compiled for the device that you've selected. To do so, click on "Processing" and then "Start Compilation".

After starting the compilation, you'll have your processors utilized for this process, and finally, if there are no errors, you'll have green ticks across all the sections as shown below.

To view the Register Transfer Logic of the half adder click on "Compile Design">"Analysis and Synthesis">"Netlist Viewers">"RTL Viewer".

You will have a New Window Displaying the Actual Circuitry. 

This is how you can see the RTL of a Circuit and there is a lot to work with this yet. In the next part of this series, we will work on how to upload the actual project to the MAX 10 FPGA and check the output with the corresponding truth table of the half adder. In the next article you will learn:

• I/O Pin Assignments
• Pin planner
• Uploading the Project to the Device using JTAG

制造商零件编号 P0638

MAX 10 PLUS EVALBOARD

Terasic Inc.

¥1,782.68

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