8V19N408 FemtoClock NG Jitter Attenuator and Clock Synthesizer

The devices has a two stages of PLL, the first stage is a jitter attenuator to the input clock signal used as an external VCXO as a high quality oscillator for getting the best possible phase noise characteristics. The second stage PLL is the one that locks on the VCXO-PLL output signal from the first stage and synthesizes the target frequency. The circuit is supplied by 2 different power supplies; a 3.3V and an external voltage regulated 3.3V. This is because of the high speed analog circuitry that the power supply pins for the VDDX pins requires isolation because it is vulnerable to noise generated by the device or board supply. The VDDQX pins are the output supply for the QCLKXn and QREFXn outputs. The QCLKXn and nQCLKXn pins are the differential clock outputs of Xn and can be configured as LVPECL, LVDS receiver and amplitude.

The 8V19N408 includes dual VCOs offering frequency plan flexibility. The typical applications of this component is in the field of communications, it is used in the line card SysncE and IEEE 1588 Slave, in wireless infrastructure base station radio card, ethernet 40GbE/100GbE, cable TV Headend equipment, radar, point-to-point microwave connections, medical imaging and other industrial applications.