The last core feature that this module will discuss is the built in 2 way, 4 word cache that is entirely transparent to the design process. There are some tips for designing code for this, but it is mostly taken care of in the architecture of the device and the compiler. This is an SRAM cache that exists for a couple reasons. First, the FRAM devices operate faster and at lower power from SRAM. Frequent usage of the cache can save time and battery life while enabling performance up to 24 MHz while FRAM access is limited to 8 MHz. Second, the FRAM is a 64-bit wide memory architecture, so some caching is necessary for the 16-bit buses in the MSP430. This graph of power consumption vs cache hit ratio is directly from the datasheet. It shows that at 8 MHz with a typical non-optimized hit ratio of 66%, the device consumes about .82 mA or 102.5 µA/MHz. This can be improved with use of smaller loops in code, and in fact some customers have already seen performance around 80µA/MHz in their applications.