This situation can definitely slow things down.  In this case, the first instruction’s result causes a non-sequential instruction to be executed.  Unfortunately, by the time this instruction is executed and this is realized, there are already 2 other instructions in the pipeline on their way to execution.  So, here, the processor has to pause and go fetch the appropriate instruction, as in cycle 4.  From there the pipeline resumes normal operation – but not before the penalty of a couple of clock cycles has been incurred.