The ARM7TDMI-S core, a commonly implemented ARM7 core, has a 3 stage pipeline and uses a Von Neumann Architecture.  The resulting core generally achieves about 1.9 clock cycles per instructions on average. The “TDMI-S” part of the core name specifies more about the core and its features.  The T indicates that the Thumb instruction set is supported, the D indicates that there are debug features available on the core, and the M indicates support for 64-bit results with an enhanced multiplier.  Additionally, the I indicates that there are EmbeddedICE logic extensions provided to support advanced debugging capabilities and the S indicates the fully synthesizable nature of the intellectual property (IP) for the ARM7 core.