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LPC29xx Microcontrollers Slide 55
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable amount of time if the processor enters an error state. The table shown here provides the different blocks that are affected by the watchdog reset. The timer registers are protected by a key register. Using a specific key and the key register, the watchdog timer registers can be accessed. There are two modes of operation: normal and debug. To prevent reset, debug mode can be used. In this mode, the watchdog can be set to interrupt the core instead of resetting it. Also, in debug mode, the watchdog can be stalled using a PAUSE feature. As mentioned before, the watchdog produces the reset via the RGU.
PTM Published on: 2011-11-02