The image shown on this slide is a snapshot of the VIC operation in its entirety. The specific registers have been mapped that are used at each stage of interrupt handling. This modified image will help in understanding the VIC interface. The INT_REQUEST registers helps the application to classify the source as an IRQ or FIQ. It will also help in setting the priority level for the interrupt. The INT_PENDING registers gather the pending bits of all the interrupt requests. Software can make use of this feature to gain a faster overview of pending interrupts than it would get by reading the individual interrupt request registers.The INT_PRIORITY mask registers define the thresholds for priority-level masking. Each interrupt target has its own priority limiter which can be used to define the minimum priority level for nesting interrupts. The INT_VECTOR register identifies for each interrupt target the highest-priority enabled pending interrupt request that is present at the time when the register is being read. The software Interrupt Service Routine (ISR) must always read the vector register that corresponds to the interrupt target. The interrupt vector content can be used as a vector into a memory based table to find the ISR address.