设置
快速交货
免运费
国际贸易术语
支付类型
市场产品
Slide 1
Slide 2
Slide 3
Slide 4
Slide 5
Slide 6
Slide 7
Slide 8
Slide 9
Slide 10
Slide 11
Slide 12
Slide 13
Slide 14
Slide 15
Slide 16
Slide 17
Slide 18
Slide 19
Slide 20
Slide 21
Slide 22
Slide 23
Slide 24
Slide 25
Slide 26
Slide 27
Slide 28
Slide 29
Slide 30
Slide 31
Slide 32
Slide 33
Slide 34
Slide 35
Slide 36
Slide 37
Slide 38
Slide 39
Slide 40
Slide 41
Slide 42
Slide 43
Slide 44
Slide 45
Slide 46
Slide 47
Slide 48
Slide 49
Slide 50
Slide 51
Slide 52
Slide 53
Slide 54
Slide 55
Slide 56
Slide 57
Slide 58
Slide 59
Slide 60
Slide 61
Slide 62
Slide 63
Slide 64
Slide 65
Slide 66
Slide 67
Product List
The first part of the image illustrates the operation of PWM0 in continuous mode. The rising and falling edges of PWM0 are controlled by the 16-bit counter and match the active and deactive registers. The match active register defines the position of the rising edge while the MTCHDEACT register defines the falling edge of the waveform. The PWM output changes when the 16-bit counter matches the values defined in the related registers. The SYNC_IN input of each PWM timer is used to reset (resynchronize) the PWM block. The SYNC_OUT can be asserted immediately after the SYNC_IN or can be delayed via the SYNDEL register. In the second part of the image, PWM0 is synchronized with PWM1. Each time a sync event is provided to PWM0, PWM1 starts or restarts after the sync delay programmed in the SYNDEL register. The image on this slide illustrates the Timer 1 carrier signal with a 50% duty cycle modulated with the internal PWM. The modulated signal typically has a higher frequency.
PTM Published on: 2011-11-02
