The specific core in the ARM7 family that will be discussed is the ARM7TDMI-S, which is based on the ARM7 core. The ARM7TDMI-S is a three-stage instruction pipeline, of Von Neumann architecture. In other words, it uses the same memory for instruction and data. The typical code executes at approximately 1.9 Clocks per Instruction (CPI). Since it is a Reduced Instruction Set Computer (RISC) machine, most instructions operate at one clock, but there are several instructions that take two or more clocks, for example, multiples and the more complex instructions. This ends up being a typical average instruction cycle time of approximately 32 nanoseconds with the core running at 60 MHz. The TDMI-S suffix on the ARM7 core is an acronym in which the T stands for Thumb instruction set, and the D refers to the debug extensions. The M refers to the enhanced multiplier on board that allows you to do 32 by 8 multiples, or you can get a full 32 by 32 with 64-bit results out of the multiplier. The ‘I’ stands for the core that has an embedded In-Circuit Emulator (ICE) logic, which allows a lot of emulation-type capabilities. Finally, the S stands for fully synthesizable. The ARM7TDMI-S is soft Intellectual Property (IP), so it can be placed on a number of new products very easily with various other peripheral makeups to virtually spin any type of processor with the ARM7 core.