Optimal pipelining occurs when there are no branches and you are able to complete an instruction pipeline. In this example, it takes six clock cycles to execute six instructions. All operations are on registers. Once the instruction pipeline is filled at cycle three, each of the following cycles executes a new instruction. In this particular example, clock Cycles Per Instruction (CPI) equals one. In other words, one instruction is executed on each clock cycle. This is not the normal case.