Let’s look at bank registers and the various modes in which they can appear. In user and system modes shown on the far left, registers r0 through r15 implement the CPSR. In FIQ mode, there is a separate set of registers, r8 through r14, and the FIQ SPSR. In each of the IRQ, Supervisor, Abort, and Undefined modes there are two registers, one dedicated to the Stack Pointer (SP) and one to the Link Register (LR). Each register is independent of the equivalent register in the corresponding modes. These registers do not need to be saved and restored when entering and leaving the various modes since they will retain their value while switching from mode to mode.