The most important figure of the POL application is the efficiency curve. First of all, the system should always be 100% efficient. Unfortunately, life is not perfect, there will always be power loss. From the last slide, Vout is lower than Vin in the POL application, so the high side MOSFET (or control FET) has short on time therefore requires faster switching so lower Qg is required. However, sync FET has longer on time, and lower Rds(on) is a must to minimize the conduction loss. The easier way is to have devices that are low Rds(on) and low Qg, but unfortunately, there is an intrinsic design tradeoff between Rds(on) and Qg. It is either having a very low Rds(on) or low Qg. The blue curve shows a typical efficiency curve. To look for high efficiency at a heavier load, a lower Rds(on) sync FET can be chosen, the result is shown in the purple curve. If low load efficiency is the preferred, a lower Qg control FET can be chosen, the result is shown in orange. In the case where performance is the priority, the design can be optimized by choosing low Rds(on) sync FET and low Qg control FET, the result is better efficiency overall.