Level translation terminations are popular in LVCMOS buffers with a high output count since they ease power supply routing to the main buffer and aid in component count reduction. The example on this slide shows a 3.3 V LVCMOS output being translated to 2.5 V through the usage of an AC coupled termination. This termination consists of a source termination, Rs, at the driver followed by a series capacitor, C1. Near the receiver is the Thevenin 50 Ω termination, whose middle bias point is dictated by the receiver. In this example, the termination results in a bias point at 1.25 V, or 50% of VDD of the receiver. Typical input structures require an LVCMOS input signal to be biased at 50% of the voltage rail, therefore this topology is incredibly common. To apply this AC coupled termination to other receiver voltages, simply follow the generic equation at the bottom of the schematic. In this equation, Vout is the output amplitude of the LVCMOS buffer (driver) and Vin is the input amplitude required at its destination (receiver). Ro and Rs are similar to previous terminations, being the output impedance and series resistance respectively. This circuit will bias the LVCMOS waveform at 50% of the VDD value at the receiver.