The parallel, or DC, termination, is a common termination for LVCMOS clock signals. The driver is terminated with a Thevenin equivalent 50 Ω termination, after the transmission line, near the receiver to minimize any possible reflections. Thevenin resistor values are determined by equations Rth and Vth, based on the bias voltage required at the receiver and trace impedance. Careful consideration is necessary when selecting the termination power supply for the Thevenin termination. Noisy power supplies can couple through this termination type and propagate throughout the entire timing tree.