One of the most challenging interfaces for mid-range FPGAs is the MIPI/D-PHY. The speeds of this interface are quite high for generic I/Os, at 4x 1.5 Gbps. Additionally, the specification defines support for both a high speed (HS) mode and a low power (LP) mode and the need to be able to support both can be a challenge for generic I/Os driving external components. Efinix dedicated a hard block that can support D-PHY v1.1 natively with no extra components. In case there are some layout challenges, Efinix can also support swapping out some of the pads, if needed. As the illustration shows, the hardened blocks “wrap” around the Core Logic elements and minimize challenges interfacing to that core logic fabric.