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Image of Efinix Trion® FPGA and How They Work - Slide11

There are dedicated pins for LVDS inputs and LVDS outputs for source synchronous buses. The LVDS pins support speeds up to 800 Mbps and gearing logic is included to simplify interfacing to the FPGA fabric for receive and transmit. Lastly, on-die terminations are included to negate the need for external resistors and simplify the layout.

PTM Published on: 2020-03-11