Currently Efinix is enabling the FPGAs with a couple of popular function blocks and hardening them inside Trion® FPGAs. These two industry standard function blocks are the MIPI/CSI core and a DDR DRAM memory core. MIPI is an industry standard organization that defines interconnects needed for high volume handset applications. D-Phy/CSI-2 is one of the most popular MIPI defined standards. CSI stands for Camera Serial Interface and is most likely the interface to the camera on the cell phone in your pocket. With so many of these camera sensors available at such a low cost, many embedded customers are using those cameras in their designs. The simple challenge lies in the fact that most processors for embedded applications, do not have a CSI port on them. This initiates a need for a bridge with enough logic to do some processing and manipulation to connect the Camera Sensor to the microprocessor of the customers choice. This is where Efinix can help out. The Trion family of MIPI/CSI enabled devices has a fully hardened controller block, so the customer does not need to add soft controller logic. These devices support the D-Phy specification up to 1.5 Gbps per MIPI lane and up to 1066 Mbps performance on the DDR3 DRAM speeds. This is leading performance for a midrange, cost focused solution. Efinix supports the CSI-2 specification for 1, 2, and 4 lanes at 1.5 Gbps and depending on the package either x16 Bit DDR DRAM Datapath or x32 on the larger packages.