Intel's 28-nm FPGA Portfolio: the Measurable Advantage

Designs are becoming increasingly complex, as system performance, power, and cost requirements continue to expand and conflict. Because a one-size-fits-all approach doesn't work, Intel has developed a 28-nm device portfolio for your unique design requirements.

In Intel’s portfolio, you'll find the broadest array of 28-nm devices, united by a common design environment designed to enhance your productivity. Whether your designs are at the high end, low end, or somewhere in between, you'll find a device that meets your requirements. What's more, you can differentiate your products without having to sacrifice one capability or advantage to gain another.

Intel’s 28-nm device families include:

Cyclone® V FPGAs, providing the industry's lowest system cost and power FPGAs
Cyclone V SoC FPGAs, integrates an ARM-based HPS
Arria® V FPGAs, balancing cost and power with performance for mid-range applications
Arria V SoC FPGAs, integrates an ARM-based HPS
Stratix® V FPGAs, delivering devices built for bandwidth

FPGA Families Overview
Development Tools
Software

FPGA Families Overview

Cyclone® V FPGAs

Developed on TSMC’s 28-nm Low Power (28LP) process, the Cyclone V family provides customers the lowest power and lowest cost at optimal performance levels needed for today’s high-volume, cost-sensitive applications. The family also includes variants with an integrated dual-core ARM®-based hard processor system (HPS) enabling over 4,000-MIPS processing performance for under 1.8 W, that deliver 40 percent lower total power versus the previous generation. Other features of Cyclone V include:

The industry’s absolute lowest-power serial transceivers, with 88-mW power consumption per channel;
800-Mbps DDR3 with integrated hard memory controllers;
PCI Express® (PCIe®) Gen2 hard intellectual property (IP) blocks with multifunction support

The Cyclone V family also offers the widest density range of 28-nm FPGAs effective for industrial, wireless, wireline, military and automotive applications.

The family comes in six targeted variants:

FPGAs

Cyclone V E FPGA with logic only
Cyclone V GX FPGA with 3.125-Gbps transceivers
Cyclone V GT FPGA with 5-Gbps transceivers

SoC FPGAs

Cyclone V SE SoC FPGA with ARM-based HPS and logic
Cyclone V SX SoC FPGA with ARM-based HPS and 3.125-Gbps transceivers
Cyclone V ST SoC FPGA with ARM-based HPS and 5-Gbps transceivers

Arria® V FPGAs

Arria V 28-nm FPGAs consume 40 percent less power than the prior generation, and enable the industry’s lowest power transceivers in midrange FPGAs, which use less than 105 mW per channel at 6 Gbps and less than 165 mW per channel at 10 Gbps. Arria V FPGAs use the lowest total power while providing optimized performance for midrange applications, such as remote radio units, Long-Term Evolution (LTE) wireless communication equipment, in-studio mixers, and 10G/40G line cards.

Arria V FPGA Family Variants:

Variant		Description
Arria V GZ FPGA		Highest bandwidth midrange FPGA wth up to 36 backplane-capable 12.5 Gbps transceivers.
Arria V GT FPGA		Lowest power mid-range FPGA for applications that require up to 20 transceivers at 10.3125 Gbps and SFF 8431 compliance
Arria V GX FPGA		Lowest power midrange FPGA for applications that require up to 32 backplane-capable 6.5536 Gbps transceivers
Arria V ST FPGA		SoC FPGA with ARM-based HPS and 10.3125 Gbps transceivers
Arria V SX FPGA		SoC FPGA with ARM-based HPS and 6.5536 Gbps backplane-capable transceivers

Stratix® V FPGAs

Stratix V FPGAs are the only FPGAs optimized on TSMC's 28-nm High Performance (28HP) high-K metal gate (HKMG) process with more than a one speed-grade advantage over competing devices. Stratix V FPGAs are the industry’s only production monolithic devices with 28-Gbps integrated transceivers. Other Stratix V features include:

The highest memory interface capability with 2,133-Mbps DDR3 support;
2.5 TMACs of digital signal processing (DSP) performance;
PCIe® Gen3 x8 support.

Combined with the added benefits of increased flexibility of partial reconfiguration and Configuration via Protocol (CvP) using the existing PCIe link, Stratix V FPGAs allow designers to increase their system performance and bandwidth while reducing power. These improvements meet the demands of high-performance applications, including Gigabit Ethernet (GbE) line cards, military radar, optical transport network (OTN), and studio server applications.

Stratix V Family Variants:

Variant		Description
Stratix V GT FPGA		Optimized for applications with 28.05 Gbps transceivers requiring ultra-high bandwidth and performance, such as 40G/100G/400G applications
Stratix V GX FPGA		Optimized for high-performance, high-bandwidth applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation at up to 14.1 Gbps
Stratix V GS FPGA		Optimized for high-performance, variable-precision digital signal processing (DSP) applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation at up to 14.1 Gbps
Stratix V E FPGA		Optimized for ASIC prototyping with 952K logic elements on the highest performance logic fabric

Development Tools

28-nm Development Kits Overview

Intel’s portfolio of 28 nm development kits dramatically increase designer productivity by offering the tools and resources necessary to get 28 nm FPGAs developed and integrated into systems. The 28 nm development kits include FPGA boards, hardware and cables, and development software that provide access to a variety of IP cores, reference designs and documentation.

Cyclone V GX FPGA Development Kit

Intel® Cyclone® V GX FPGA Development Kit (DK-DEV-5CGXC7NES) offers a quick and simple approach to develop low-cost and low-power FPGA system-level designs to achieve rapid results. This kit supports a myriad of functionalities such as:

FPGA prototyping
FPGA power measurement
Testing of XCVR I/O signal quality, up to 3.125 Gbps
- PCI Express® (PCIe®) x4 lane with ~1,000 MBps transfer rate
- Endpoint or rootport

Arria V GX Starter Kit

The Intel® Arria® V GX Starter Kit (DK-START-5AGXB3NES) provides a complete design environment that includes all the hardware and software you need to develop cost-sensitive FPGA applications immediately. The development kit is RoHS compliant. The development kit features the following:

Arria V GX FPGA—360KLE, F1152 package, 24X6.5G XCVRs, C5 speed grade
One I/O expansion slot—one high-speed mezzanine card (HSMC) connector
256 MB of SDRAM memory
High-definition multimedia interface (HDMI) and serial digital interface (SDI) connections
SMAs

Stratix V GX FPGA Development Kit

The Intel® Stratix® V GX FPGA Development Kit (DK-DEV-5SGXEA7N) provides a complete design environment that includes all the hardware and software you need to begin developing FPGA designs immediately. The development kit is RoHS compliant. You can use this development kit to do the following:

Develop and test PCI Express® (PCIe®) designs at data rates up to Gen3 using the PCIe short card form factor-compliant development board
Develop and test memory subsystems for DDR3, QDR II+, or RLDRAM II memories
Use the high-speed mezzanine card (HSMC) connectors to interface to one of over 35 different HSMCs provided by Intel partners, supporting protocols such as Serial RapidIO®, 10-Gbps Ethernet, SONET, CPRI, OBSAI, and others

Transceiver Signal Integrity Development Kit, Stratix V GX Edition

The Intel® Stratix® V GX Transceiver Signal Integrity (SI) Development Kit (DK-SI-5SGXEA7N) provides a platform for electrical compliance testing and interoperability analysis. The accessibility to multiple channels allows for real-world analysis as implemented in the system with transceiver channels available through SMA and popular backplane connectors. You can use this development kit to perform the following tasks:

Evaluate transceiver link performance from 600 Mbps to 12.5 Gbps
Generate and check pseudo-random binary sequence (PRBS) patterns via a simple to use GUI (does not require the Quartus® II software)
Access advanced equalization to fine tune link settings for optimal bit error ratio (BER)
Perform jitter analysis
Verify physical medium attachment (PMA) compliance to 10GbE, 10GBASE-KR, PCI Express® (PCIe®)(Gen1, Gen2, and Gen3), Serial RapidIO®, Gigabit Ethernet, 10-Gigabit Ethernet XAUI, Common Electrical I/O (CEI) 6G, CEI-11G, high-definition serial digital interface (HD-SDI), Interlaken, and other major standards
Use the built-in high speed backplane connectors to evaluate custom backplane performance and evaluate link BER

DSP Development Kit, Stratix V Edition

The DSP Development Kit (DK-DEV-5SGSMD5N), Stratix® V Edition provides a complete design environment that includes all the hardware and software you need to begin developing DSP-intensive FPGA designs immediately. The development kit is RoHS compliant. You can use this development kit to do the following:

Develop and test PCI Express® (PCIe®) designs at data rates up to Gen3(1) using the PCIe short card form factor-compliant development board
Develop and test memory subsystems for DDR3 or QDR II memories
Use the high-speed mezzanine card (HSMC) connectors to interface to one of over 35 different HSMCs provided by Intel partners(2), supporting protocols such as Serial RapidIO®, 10-Gbps Ethernet, SONET, CPRI, OBSAI, and others

Software

	Quartus II design software If you’re looking for a design environment that will quickly move you from concept to creation, choose Intel’s Quartus® II design software. Number one in performance and productivity for CPLD, FPGA, and HardCopy® ASIC designs, Quartus II software offers complete, automated system definition and implementation, all without requiring lower-level HDL or schematics. This capability—plus its seamless integration with leading EDA software tools and flows—will help turn your ideas into working systems in minutes.
	IP Core Intel offers a broad portfolio of easy-to-use IP cores. These IP cores are high-quality “building blocks” that you can drop into your system designs, avoiding the time-consuming task of creating complete designs from scratch. Easy-to-use, pre-verified, and configurable, Intel® IP cores are optimized for the latest Intel devices and are fully supported in Quartus® II design software.
	ModelSim ModelSim is a widely-used logic simulation tool for verification and debugging of digital circuits. Intel® provides a version of ModelSim software, which includes libraries for Intel's FPGA devices. Users of the Quartus II Web Edition software should also download the ModelSim package.
	Qsys The Qsys system integration tool in Quartus® II software saves time and effort in the FPGA design process by enabling faster system development and design reuse. Qsys automatically generates interconnect logic to connect intellectual property (IP) functions and subsystems. Qsys replaces the SOPC Builder tool for new designs.
	DSP Builder Intel’s DSP Builder technology allows you to go from system definition/simulation using the industry-standard The MathWorks/Simulink tools to system implementation in a matter of minutes.
	The Nios® II embedded processor When you’re poised to capture an early-to-market advantage with your novel idea, turn to Intel’s Nios II embedded processor to give you a jump on the competition. By allowing you to drag and drop the precise mix of processors and peripherals needed to build your system, the versatile 32-bit Nios II processor equips you to create an exact-fit processor system in just minutes.